The present invention relates in generally to a nonvolatile semiconductor memory device and a method for fabricating the same, and more particularly to an electrically erasable and programmable read only memory (hereinafter "EEPROM") cell improved in programming operation and erasing operation and suitable for very large scale integration, along with a fabrication method for the same.
An EEPROM cell, which has a field effect transistor structure, is operated by use of a floating gate overlying an insulating layer atop the channel region which is formed between a source region and a drain region in a substrate, and a control gate overlying another insulating layer atop the floating gate.
Such EEPROMS have been used in limited fields, but as an interest in flash memory grows, its application fields have continued to expand.
Hereinafter, conventional EEPROM cell structures are to be briefly discussed with reference to several figures, along with problems accompanying these structures.
FIG. 1 shows one of the most conventional EEPROM cell structures. As shown in this figure, the EEPROM cell is structured to have a floating gate 4 between a substrate 1 and a control gate 6. The cell is considered to be programmed if the threshold voltage of the cell is increased as hot electrons are injected into the floating gate 4. On the other hand, the information is considered to be erased if the threshold voltage of the cell returns to its original state as the electrons are removed from the floating gate. The so-called "hot electron" means the free electron which is emitted from the metal plate of hot electron, when the metal plate is heated. The hot electrons are applied to a vacuum tube. In the meanwhile, carriers that are injected into a depletion layer are accelerated by a high field, and some of them may gain enough energy to cause impact ionization. These carriers have more energy than the thermal energy and are called "hot carriers".
In the EEPROM cell having the structure of FIG. 1, a high voltage is applied to a drain 2b to generate avalanche hot electrons. These avalanche hot electrons are injected into the floating gate 4, so that the cell is programmed. On the other hand, for the purpose of erasing the information, a high voltage is applied to a source 2a to emit the injected electrons from the floating gate through a thin tunneling oxide film.
Referring now to FIG. 2, another conventional EEPROM cell is shown. The EEPROM cell of FIG. 2 is structured so as not to include a tunneling oxide film which exists in FIG. 1. The programming and erasing operation is carried out in a manner similar to that for the cell structure of FIG. 1. This structure of EEPROM cell is used for flash memory.
In the aforementioned conventional cell structures, a high electric field has to be generated in the drain region 2a in order to improve a programming characteristic, whereas, for the better erasing characteristic, it is required to improve the junction breakdown characteristic so as not to generate junction breakdown when applying a high voltage to the source region 2b.
In an effort to improve those characteristics, an EEPROM cell structure has been disclosed in U.S. Pat. No. 4,972,371, which is schematically shown in a cross sectional view in FIG. 3. As illustrated in this drawing, there is formed a p.sup.+ region 7 wherein impurities are doped in a high concentration beside a drain region 2b, in order to give rise to electric field, whereas there is formed an n.sup.- region wherein impurities ante doped in a low concentration beside a source region 2a, in order to improve the junction breakdown characteristic.
However, the EEPROM cell structure suggested in the aforementioned patent has disadvantages such as that the source and the drain are formed separately and differently, so that the fabrication method becomes complicated and even troublesome. For example, a photolithograph process is to be carried out in order to fabricate the EEPROM cell structure of FIG. 3, at least two times as many as for those of FIGS. 1 and 2.